Archive for May, 2009

Power, Transitions, Stimulus and Standard Cells

May 12, 2009 at 6:51 am · Filed under CMOS, General, Low Power, Miscelaneous, Open Questions, semicustom design ·Tagged , , , ,

If dynamic power consumption is all about transitions, and transitions are all about stimulus, … what about stimulus?

Long time ago I had to characterise in power a standard-cell which I designed using full-custom tools. It was a full-adder. To get the dynamic switching power figure of one output for a given output load I ran some SPICE simulations. The stimulus to the three-input (a,b and d) two-output (sum and carry) cell was given by

{1->4->6->7->3->5->2->1->4->6..}.

Thus, the inputs take the logical values {a,b,d}={0,0,1}->{1,0,0}->{1,1,0}->{1,1,1}->… and the carry output, c, changes as follows

c={0->0->1->1->1->1->0->…}.

As it can be seen, ONLY two transitions occur in c (as transitions I mean changes from 0->1 or 1->0). So, I was able to generate just 2 transitions out of 7 states (28.6%) with this sequence. My full-adder was not really much exercised!
Now, is this input sequence “random”? Well, it is a PN-sequence (PN stands for pseudo-noise) generated by a max-length linear-feedback shift-register (LFSR) and as such it complies with all the properties a sequence must have according to S. Golomb to be “random”. Is it not random enough? Is it possible to increase the number of transitions by proper stimulus assignment?

Then, I looked at two different 4-state max-length LFSR: the first one gave 4 transitions out of 15 states, and the second one gave 6 out of 15. A change of +13%. I thought for a while and realized that: if dynamic power consumption is all about transitions and, transitions is all about stimulus, then, how can I define the “right” stimulus to my cells?

Ok, Databooks of standard-cell libraries give dynamic power figures normalized to the frequency of the signal, that is, in µW/MHz. But now, how can I define the frequency of a periodic signal which does not have 50% duty cycle? Would it be a solution to use {1->4->6->7->1->4->…}?

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Gated Clock Dividers

May 7, 2009 at 8:41 am · Filed under finite state machine, semicustom design

One of the most well-known structures in digital design is a “Clock divider by 2″,

ckdiv21

where the negated output Q of a D-Flip Flop is connected to its D input. Thus, CKdiv2 shows half of frequency of clock CK. If we want to gate this output by a signal x, then we can do the following

ckdiv2whenx3which is straightforward. So far it seems very intuitive. Now, we want a clock divider by 4 and gated by a signal x. One could try to cascade the previous structure and then try to incorporate an AND gate to provide a gated clock. Ok, I am not a very good friend of trial & error methods and I prefer the more systematic methods in circuit design. In this case, my favourite one is the state machine synthesis. My finite state machine (FSM) looks like this,

fsm_ckdiv4whenx2

where X stands for “don’t care”, that is, either 1 or 0. Note that we have chosen the output to be S0. Thus, we have a 2 D-Flip Flop (DFF) solution to our problem. The synthesis of a FSM follows straightforward: 1) build a logic table with x, S0 and S1 as inputs and, S0_next  and S1_next (D input of DFFs) as outputs, 2) compute per Karnaugh the logic function of S1_next and S0_next.

The resulting structure follows,

ckdiv4whenxwhich is not so intuitive.

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