A Manchester encoder is that one which encodes logic bits –usually given as a non-return-to-zero (nrz) signal– into signal transitions. For example, a logic one (zero) is encoded as a positive (negative) edge. Thus, the encoded signal has zero DC and provides enough transitions to recover easily a clock (obviously, at the cost of doubling the bandwidth). A Manchester decoder (MD) is that one which decodes the encoded signal back to nrz.
My MD is an all-digital one, it has a hard decision input, a feedforward structure, and is based on an over-sampling & counting algorithm. Since a Manchester encoded signal is basically a signal of 4 alternating signal states (short/long ones/zeros), the idea is first to take a decision on whether a short or long one/zero was sent and then based on this information decode into nrz.
The following Figure shows the structure of the MD.
The Pre-processing block converts the Manchester encoded signal mdin –1-bit hard decision– into datain and bitsynchin and generates clk_transition (a tick everytime a transition on mdin occurs). The mdin is oversampled by 16 and the number of adjacent ones/zeros is counted. Based on the resulting count the block takes a decision: short or long one/zero. The decision intervals can be made programmable. For simplicity, we call a short one/zero a SINGLE one/zero (S1/S0) and, a long one/zero a DOUBLE one/zero (D1/D0). Thus, datain represents mdin as a sequence of symbols taken from the following alphabet: S0, S1, D0 and D1. Similarly, bitsynchin is just a subset of datain and gives information about mdin being a SINGLE or a DOUBLE, that is, a sequence of symbols from the following alphabet: S, D.
The use of clk16x, that is, an oversampling factor of 16 is arbitrary. It is worth emphasizing that if T is the bit period and Ts the sampling period, Ts/T does not be necessarily an integer, it can be rational. Also, note that the higher the oversampling frequency, 1/Ts, the more robust the algorithm works — obviously at the cost of power–. On the other side, just the Pre-processing block runs at the highest clock. The Finite State Machines (FSM) run at the slower derived clock clk_transition. In the following, both FSMs in the Mealy sense are shown,
where transitions are labelled with /1 and /0 denoting output bit 1 and 0, respectively. A transition occurs from A to B if the input signal is equal to B. In the case of FSM Bit Synch., a transition occurs from Axx to Bxx if the input signal is equal to B (not attending to the subscript). To understand the FSMs you will need to think on terms of SINGLEs and DOUBLEs (to exercise I recommend to use the following timing diagram). Note that nrz is synchron to the positive and negative edges of clk_nrz.
I do believe a decoder like this one is more robust than one based on a mid-bit finder –but, I’ve not verified this yet–. It would be great to get some feedback from the engineers out there. Furthermore, I do think one can combine both FSMs into just one and save some power. Interestingly enough, it takes more states –8 instead 4– to generate the clock signal clk_nrz than the data nrz, even though the input information needed is less — [D,S] instead [D0, D1, S1, S0]–.
This post may not seem to be related to arithmetic, but I do believe arithmetic has to do a lot with finite state machines (FSM), and, an all-digital Manchester decoder is precisely an FSM (or two!).
