One of my favorite adders is the carry increment adder (CIA). In my opinion, if you use static CMOS logic this adder provides the best trade-offs in power, area and delay.
If you do semi-custom design (standard-cell-based designs) you find/obtain surely this adder structure under the DesignWare Library. For more information I recommend looking at the work of Reto Zimmerman http://www.iis.ee.ethz.ch/~zimmi/.
If you are a full-custom designer you may want to know how a CIA can be implemented. In the following we illustrate by means of example: a 16-bit CIA with a block-size scheme {1,2,3,4}. Its prefix structure is shown below,
where the coloured dots are prefix operators:
Note that the red dots need to compute only the carries, that is 
The most important property of this adder is its regularity which translates into a regular layout with as few as two different leaf-cells! Looking at the bit-slices it is apparent that there are only two types of leaf-cells:
- leafcell 0 (lc_pa0): the ones with just one prefix operator -only a red dot- (bit-weights 1,2,4,7 and 11) and,
- leafcell 1 (lc_pa1): the ones with two prefix operators -yellow and red dots- (3,5,6,8,9,10,12,13,14 and 15).
The routing is clear from the prefix structure.
Thus, leafcell 1 (lc_pa1) can be implemented as
and leafcell 0 (lc_pa0) as
